1. Field of the Invention
The present invention relates to a method for fabricating a memory cell, in particular, a method for fabricating a flash memory cell.
2. Description of the Prior Art
Complementary metal oxide semiconductor (CMOS) memory is generally categorized into two groups: random access memory (RAM) and read only memory (ROM). RAM is a volatile memory, wherein the stored data disappears when power is off. On the contrary, turning off power does not affect the stored data in a ROM.
In the past few years, market share of ROM has been continuously expanding, and the type attracting the most attention has been flash memory. The fact that a single memory cell is electrically programmable and multiple memory cell blocks are electrically erasable allows flexible and convenient application superior to electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and programmable read only memory (PROM). Furthermore, fabricating flash memory is cost effective. Having the above advantages, flash memory has been widely applied in consumer electronic products, such as digital cameras, digital video cameras, mobile phones, notebooks, personal stereos and personal digital assistants (PDA).
Since portability of these electrical consumer products is strongly prioritized by consumers, the size of the products must be minimal. As a result, capacity of flash memory must increase, and functions must be maximized while sizes thereof are continuously minimized. Having an increased amount of access data, capacity of memory cells has been enhanced from 4 to 256 MB, and even 1 GB will become the market trend in the near future. Masks are essential in conventional processes for fabricating flash memory, even for the most critical process of floating gate and control gate.
Conventional process for a split gate flash memory cell is further explained with references to FIGS. 1Axcx9c1H. In FIG. 1A, using a p type substrate 100 as an example, local oxidation (LOCOS) is used to form a field isolation region 105. An active area 107 is separated from the field isolation region.
FIG. 1B is a cross-section taken from line A-Axe2x80x2 in FIG. 1A. On the surface of the substrate 100 within the active area 107, silicon oxide is used to form a first insulating layer 110. Next, polysilicon is deposited by chemical vapor deposition on the first insulating layer 110. Suitable amount of dopant is doped in the polysilicon to form a first conductive layer 115. Then, silicon nitride is deposited on the first conductive layer 115 to form a first masking layer 120, used as hard mask in the following step.
Part of the first masking layer 120 is removed to define a first opening 125 and to expose the surface of the first conductive layer 115, as shown in FIG. 1C. The first masking layer 120 remaining is represented by the remaining first masking layer 120xe2x80x2.
Oxidation is then performed to transform the surface of the exposed first conductive layer 115 to a floating gate oxide 130, as shown in FIG. 1D.
In FIG. 1E, isotropic etching is used to remove the first masking layer 120, followed by using the floating gate oxide 130 as a hard mask to carry out anisotropic etching. At this step, part of the first conductive layer 115 and the first insulating layer 110 are removed, leaving the first conductive layer 115 and the first insulating layer 110 underneath the floating gate oxide 130, and exposing the surface of the substrate 100. The remaining first conductive layer 115 forms the floating gate 136, and the remaining first insulating layer 110 is represented by first gate insulating layer 112. Poly tip 138 is formed when forming the floating gate 136, and this poly tip 138 is to discharge the floating gate 136 when erasing memory in the flash memory. Next, chemical vapor deposition is used to form a second insulating layer 132, silicon oxide covering the substrate 100, the surface of the floating gate oxide 130, the floating gate 136 and the sidewalls of the first gate insulating layer 112. Thickness of the second insulating layer 132 is 100xcx9c250 angstroms.
A second conductive layer 135, for example, doped polysilicon, is formed to cover the surface of the second insulating layer 132, as shown in FIG. 1F.
Photolithography and etching are then performed to remove part of the second conductive layer 135 and second insulating layer 132, as shown in FIG. 1G, to form a second opening 142 and a third opening 144. The remaining second conductive layer 135 is the control gate 170 and the remaining second insulating layer 132 is the second gate insulating layer 155.
N-type dopants, such as P or Ar, are doped into the substrate 100, as shown in FIG. 1H, to form a source 180 in the substrate 100 within the second opening 142. Next, an oxide layer (not shown) is formed to cover the surface and sidewalls of the floating gate 170, the sidewalls of the second gate insulating layer 155, the surface of the floating gate oxide 130, the floating gate 136 and the sidewalls of the first gate insulating layer 112. Etching is then performed to remove part of the oxide to form insulating spacers 150 on the sidewalls of the second opening 142 and the third opening 143. Then, N-type dopants, such as P or Ar, are doped into the substrate 100 to form a drain 190 in the substrate 100 within the third opening 143. This completes the fabrication of a flash memory cell.
Conventionally, a floating gate oxide is formed on a conductive layer made of doped polysilicon, followed by anisotropic etching to remove the doped polysilicon conductive layer not covered by the floating gate oxide. By doing so, the doped polysilicon conductive layer underneath the floating gate oxide forms the floating gate. When integration of memory increases rapidly, all elements sizes must decrease. Therefore, for traditional methods, sharpness of floating gate tip is no longer satisfactory because of the oxidation used to form a floating gate insulating layer.
There are three main features for this invention:
1. A conductive layer is formed on the substrate, followed by forming a pad layer on the conductive layer. The pad layer is defined to form an opening, followed by forming a conductive spacer to be used as a poly tip. Next, insulation material is filled to form a gate insulating layer. Using the gate insulating layer as hard mask, the conductive layer not covered by this hard mask is removed, such that the poly tip and the conductive layer underneath together form a floating gate. The formation of the conductive spacer is accomplished by a fully-developed anisotropic etching, thus ensuring the poly tip formed is sharper than the one conventionally made. Process is easier to control as well. Consequently, the method provided in this invention will not be limited by line width.
2. Since the floating gate of the invention is formed by self-alignment, the floating gate can be accurately formed on the active area between shallow trench isolation. Misalignment due to the formation of the floating gate during photolithography will not deviate the floating gate from the predetermined position. In conventional split gate Flash, if the floating gate is not accurately formed in its position, because of misalignment during photolithography, gap occurs between the floating gate and the shallow trench isolation, resulting in dysfunction of the shallow trench isolation.
3. Shallow trench isolation and the first gate insulating layer are formed simultaneously for the method of this invention, simpler than conventional methods.
The invention provides a method for fabricating a flash memory cell, which comprises the following steps: providing a semiconductor substrate; forming a first insulating layer on the substrate; forming a first conductive layer on the first insulating layer; forming pad layer on the first conductive layer; removing part of the pad layer to form a first opening and expose the surface of the first conductive layer; forming a second conductive layer on the surface of the pad layer and sidewalls and bottom of the first opening; removing the second conductive layer covering the surface of the pad layer and the bottom of the first opening, thus the second conductive layer on the sidewalls of the first opening forms the conductive spacer, wherein the spike part on the top of the conductive spacer is the tip; removing sequentially the pad layer, first conductive layer, first insulating layer and substrate to form a second opening; forming a second insulating layer to fill the first opening and the second opening, which forms a first gate insulating layer and shallow trench isolation respectively; removing the remaining pad layer to expose the surface of the first conductive layer; using the first gate insulating layer as hard mask to sequentially remove the first conductive layer and the remaining first insulating layer not covered by the first gate insulating layer and the conductive spacers, and keeping those at the bottom part of the first gate insulating layer and the conductive spacer, wherein the remaining first conductive layer is the floating gate, the remaining first insulating layer is the second gate insulating layer, and the first gate insulating layer, conductive spacers, floating gate and the second gate insulating layer are represented by gate region; forming a third insulating layer to cover the surface of the substrate and the surface and sidewalls of the gate region; forming a third conductive layer to cover the third insulating layer; removing the third conductive layer and the third insulating layer on top and side parts of the gate region to form a third opening, simultaneously forming a fourth opening on the other side of the gate region, wherein the remaining third conductive layer forms a control gate and the remaining third insulating layer forms a tunneling oxide; forming source in the surface of the substrate at the bottom of the third opening; forming a fourth insulating layer to cover the surface of the control gate and evenly covering sidewalls and bottom parts of the third opening and the fourth opening; partially removing the fourth insulating layer and forming insulating spacers on the sidewalls of the third opening and the fourth opening; and forming a drain in the surface of the substrate at the bottom of the fourth opening.